Two quantum computers assembled from several suppliers’ parts began operating in 2026, one in Colorado and one in Oxfordshire. In their announcements, neither group behind them published gate error rates or benchmark results. Q-PAC, declared fully operational by its partners in March, combines a QuantWare processor, Qblox control electronics, Maybell Quantum refrigeration and wiring, and Q-CTRL calibration software. In April, TreQ, an Oxfordshire-based company that builds and operates such systems, opened a testbed with two options each for the processor, the control electronics and the calibration software, eight combinations in all.
Quantum open architecture is the industry’s name for this approach, in which a buyer assembles a quantum computer from interchangeable parts made by different suppliers instead of buying one vendor’s integrated machine. Quantum systems integration is the engineering work of turning such parts into a working computer, from choosing and connecting them to calibrating and operating the assembly. QuantWare, a Dutch processor maker that sells into this market, said in May that it had shipped processors to more than 50 customers across 20 countries.
Buyers already pair control electronics and refrigerators from different suppliers and use open compiler formats, but among the interfaces reviewed here calibration has a published specification only for pulse jobs and links between processor modules have none, so they still face lock-in and schedule risk in those two layers.
Disclosure: Quantum Observer’s Editor-in-Chief Marin Ivezic is the founder and CEO of Applied Quantum, a quantum systems integration and consulting firm.
Interfaces a second supplier can build against
Control electronics
A superconducting processor runs on microwave and voltage pulses sent down coaxial lines from racks of electronics at room temperature. Those signals can be specified and checked with standard laboratory instruments, so a company can sell control electronics for a processor it did not make. In Q-PAC, Qblox electronics drive a QuantWare processor with 17 physical qubits, the individual quantum bits fabricated on the chip. TreQ’s consortium planned its testbed around processors from Rigetti and QuantWare, driven by control systems from Quantum Machines and Qblox.
Refrigeration
Superconducting and silicon spin qubits work inside dilution refrigerators that cool them to within a few thousandths of a degree of absolute zero by circulating a mixture of helium-3 and helium-4. Makers such as Bluefors sell these machines as instruments, rated by their lowest temperature and by how much heat they can remove at the coldest stage.
A processor maker can design its mounting and wiring against those ratings. Maybell supplied the refrigeration for both Q-PAC and TreQ’s testbed. In a companion analysis, Quantum Observer maps the supply chain behind these refrigerators, from their makers to helium-3 and export controls.
Compiler formats
Above the hardware, programs reach machines through shared formats. OpenQASM is an open language for describing quantum circuits, published by its contributors.
The QIR Alliance, part of the Linux Foundation’s Joint Development Foundation, maintains QIR, an intermediate representation. An intermediate representation is the machine-readable form a compiler produces between a programmer’s code and a particular machine’s instructions. The alliance’s steering members include Microsoft, NVIDIA, Quantinuum and Rigetti Computing.
The customer-facing side of this boundary is the most settled part of the stack. Amazon offers machines from five hardware makers through one service, Amazon Braket. At the UK’s National Quantum Computing Centre (NQCC), Oxford Ionics accepted jobs in what the center called, in its October 2026 report, “industry-standard OpenQASM and Qiskit formats.”
Interfaces set by one company
The GPU link
An error-corrected quantum computer needs conventional processors close enough to act on its measurements within microseconds. In October 2025, NVIDIA introduced NVQLink and described it as “an open system architecture for tightly coupling the extreme performance of GPU computing with quantum processors.” The company said 17 quantum processor builders, five control-system builders and nine U.S. national laboratories supported it. Quantinuum, a builder of its own trapped-ion machines, said it was integrating NVIDIA’s GB200 with its Helios computer through NVQLink.
In IBM’s reference architecture for joining quantum processors to supercomputers, published in March 2026, the authors listed NVQLink beside two alternatives, Ultra Ethernet and UALink, as candidate interconnects. In September, Xanadu and AMD released Backline, open-source software that connects Xanadu’s PennyLane programs to AMD processors, and described it in a Xanadu preprint. NVIDIA calls NVQLink open and has lined up other companies to support it. It remains NVIDIA’s own specification, and no independent standards body backs it.
The decoder link
A decoder is the conventional processor that reads the results of an error-corrected machine’s repeated checks, called syndromes, and works out which corrections to apply. It must keep pace with the quantum hardware, so it is tied closely to the control electronics that collect the syndromes. Riverlane, a British error-correction company, has written a specification for that boundary, called QECi. The company describes QECi as “a standard way of communicating” between a control system and the error-correction stack, one that works “by defining the data format, runtime states and parameters” for error-correction messages.
Riverlane distributes QECi through a download form under terms of use and watermarks each copy with the recipient’s name and organization. It has released only the physical layer, QECIPHY, as open source. Riverlane says Qblox “is working with Riverlane to adopt QECi.”
In September, Qblox and Riverlane timed a full correction loop over QECi at 6.886 microseconds for the smallest of the four codes they tested and 11.886 microseconds for the largest. Qblox counted readout integration, the time spent collecting each qubit’s measurement signal, in those figures. The companies fed the loop emulated qubit data and connected no quantum processor.
A decoder from one company has also been integrated with another company’s processor. The NQCC reported that Rigetti’s testbed at the center was integrated with Riverlane’s Deltaflow system for real-time error correction.
In a May 2025 preprint estimating the machine needed to break 2048-bit RSA encryption, Google’s Craig Gidney assumed “a control system reaction time of 10 microseconds,” the delay between measuring an error check and acting on the decoded result. Qblox and Riverlane came in under that time only for their three smaller codes. Gidney also modeled the machine as one uniform square grid of qubits with nearest-neighbor connections and no boundaries between modules.
Layers without a full interface
Calibration
A quantum processor drifts out of tune, so automated routines must periodically measure and reset the settings that make each gate accurate, such as pulse frequencies and shapes. The authors of the OpenQASM specification wrote, “By their very nature calibrations are transient and unique to a target system.” They defined a syntax for writing down calibrated gates and expected the calibrations themselves to come from “the target system provider.”
Quantum Machines, an Israeli control-electronics maker, said in May 2025 that “calibration has emerged as one of the most critical bottlenecks in scaling quantum computers.” It estimated that calibrating a superconducting computer with 100 physical qubits from scratch “can take up to two days.”
The company released its calibration framework, QUAlibrate, as open source but describes it as “built for OPX hybrid controllers,” its own hardware, with calibration steps “implemented as QUA programs” in its own control language. On the same page, Quantum Machines says QUAM, the software model of the machine that QUAlibrate builds on, enables “more flexible, hardware-agnostic calibration workflows.” The company names as supported hardware only its OPX controllers, alone or inside NVIDIA’s DGX Quantum. A calibration routine written that way is tied to Quantum Machines hardware.
On May 27, 2026, Quantum Machines reported that a team working onsite at Rigetti had used QUAlibrate and its OPX1000 control stack to calibrate and operate Rigetti’s 9-qubit Novera processor. It reported a median two-qubit gate fidelity of 99.5% across all 11 qubit couplings and a median single-qubit fidelity of 99.93%. Fidelity measures how closely an operation matches its ideal, where 100% is perfect.
IBM moved the other way in November 2024, when it announced that it would remove pulse-level control, the ability to program the raw pulses behind each gate, from all its processors on February 3, 2025. IBM said its new fractional gates covered “the predominant use case described by users for pulse-level control.” The company wrote in its changelog for that date that “Pulse-level control on all IBM Quantum processors has been removed.” Outside users lost access to the layer at which IBM calibrates its gates.
TreQ’s consortium has proposed a shared interface for this layer. It wrote OAQ, a specification published under the Apache 2.0 license, as a common format for “low-level jobs,” the pulse schedules that calibration software sends to control electronics. Q-CTRL and Qruise, two calibration-software companies, have built it into their commercial products. TreQ demonstrated it on Quantum Machines and Qblox hardware.
In version 0.1.0, the consortium defined a format for pulse schedules but none for calibration results or device parameters.
An assembled machine’s accuracy therefore depends on calibration, the layer where a buyer has the least choice. A buyer who takes a processor from one supplier and electronics from another inherits the whole calibration problem. The supplier whose software can calibrate the pair controls the schedule.
Links between modules
IBM plans to build its larger machines by joining processors with couplers. Its roadmap includes Cockatoo, a system expected in 2027 that “will entangle two Kookaburra modules using ‘L-couplers,'” on the way to Starling, a machine planned for 2029 to run 100 million operations on 200 logical qubits. A logical qubit is an error-protected unit of information encoded across many physical qubits.
IBM said in August 2026 that its new modular cryogenic architecture is designed to scale into the system “required to link hundreds of quantum chips” into one computer. By the time Starling is delivered, the company plans “for each cryogenic module to house thousands of qubits.”
An L-coupler, IBM’s term for a long-distance coupler, joins qubits on processors in separate modules. In an October 2026 preprint, IBM researchers wrote that such links “must support coherent quantum operation over meter-scale distances.” They reported four L-couplers, each built around 80 centimeters of superconducting aluminum coaxial cable, linking two Nighthawk processors with 120 programmable physical qubits each.
Gates between qubits on the two processors had a mean fidelity of 94.75% and a best of 96.42%. The researchers moved qubit states across the couplers with a mean fidelity of 99.00% and a best of 99.29%.
Code designers are planning for noisy seams between modules. In an October 2026 preprint, Google researchers simulated codes spread across small modules and set the error of gates between modules at 1%, ten times the error inside them. They reported “only a modest increase in logical error rate.” IBM’s best measured gate across an L-coupler had an infidelity of about 3.6%, a benchmark figure that is not the same quantity as the simulated error probability.
IBM’s researchers traced most of that error to the extra steps needed to route each gate through the couplers’ own qubits. In their error budget for the gate, two state transfers accounted for 53% and three local two-qubit gates for 40%. They wrote that building the coupler elements directly into the processors’ own qubits would remove those steps “and would therefore substantially increase inter-module operation fidelity.”
In February 2025, a University of Oxford team reported in Nature a gate teleported between two trapped-ion modules about 2 meters apart, with 86% fidelity.
Each of these links joins processors from the same maker or laboratory. IonQ said in April that it had linked two of its own trapped-ion computers with photons, but it gave no fidelity, rate or distance for the link. Cisco’s prototype switch, meant to route quantum signals between machines that encode them in different ways, has been tested with only one encoding.
Through its Heterogeneous Architectures for Quantum (HARQ) program, DARPA is funding “high-fidelity interconnects that support communication between different types of qubits.” The agency gave its teams 24 months from April 2026 to work on the design principles, tools and components.
IonQ and Duke University researchers reported a link between two types of qubit in an October 2026 preprint. They entangled a trapped-ion qubit with a silicon-vacancy memory in diamond about 1,030 times a second, at 87.9% fidelity. Both ends of that link are IonQ technology.
The case for integration
The companies furthest along supply the strongest objection to this reading. DARPA lists six companies, Atom Computing, Diraq, IBM, IonQ, Microsoft and PsiQuantum, in the final stage of its Quantum Benchmarking Initiative. The agency designed the initiative to verify whether any approach can reach utility-scale operation by 2033. Each of the six companies designs its own qubits.
Pranav Gokhale, Infleqtion’s chief technology officer, said in September that his company was integrating its error-correction software with NVIDIA’s “because the code and the machine must be designed together.” IBM’s researchers ended their reference architecture with a phase in which “fully co-designed quantum-HPC systems emerge.” If co-design across code, chip and decoder is the better route to fault tolerance, the vendors that build everything will set the interfaces that fault-tolerant machines use. Open architecture would then be used more in testbeds and national programs than in the machines that set records.
Companies that design their own qubits still buy parts from other suppliers where an interface exists. Researchers from Diraq, one of the six, and imec measured their spin qubits in a Bluefors refrigerator at a base temperature of 10 millikelvin.
The integrated vendors keep to themselves the two layers without a full interface, calibration and the links between their own modules. Those two layers are the source of both the vendors’ advantage and a buyer’s lock-in.
Who is paying for interfaces
The open integration projects described here all have public backing. The NQCC spent £30 million, with Innovate UK, on seven testbeds from seven companies using five kinds of qubit. In its October 2026 report, the center wrote that it had been “both ambitious and challenging to deliver, deploy and commission the seven testbed systems within such an accelerated timeframe.”
The center had aimed to “deliver two thirds of testbeds that are functional against target performance criteria by 31 March 2025,” and it met that goal only in part. “Some of the contracts were extended, but all were delivered during 2025,” the center wrote. Some suppliers reported “difficulties in accessing enabling technologies” such as packaging, electronics testing and cloud provision.
In May 2021, Germany’s aerospace research center, DLR, said that the federal economics ministry had granted it 740 million euros in funding over the next few years. DLR planned to build prototype quantum computers “with different architectures” in a consortium with companies and research institutes, and said about 80% of the money would go to industrial partners. TreQ’s testbed is part of Innovate UK’s Quantum Mission Pilot. Q-PAC runs at a hub that the Commerce Department designated under its Tech Hubs program.
In each of these programs, a public institution funds or hosts the integration work, often alongside commercial integrators. Quantum Observer found no contract term requiring conformance to a named interface in the program documents it reviewed. A buyer that wrote OAQ, QECi or a successor into a procurement would turn a vendor’s specification into a market requirement.
What would confirm or overturn this
Four developments would show the unsettled layers moving toward shared interfaces. Each would appear in a public document.
- A published format for calibration results and device parameters, so that calibration records and routines transfer when a machine’s control electronics change, leaving less to remeasure. OAQ’s authors are closest. They have already used version 0.1.0 to move calibration software between two control systems.
- A decoder qualified on a quantum processor it was not written for, with a published round trip inside the 10-microsecond reaction time that Gidney assumed in his RSA estimate. Qblox and Riverlane met that time on emulated data for the three smaller of the four codes they tested.
- A procurement, public or commercial, that makes conformance to a named interface such as OAQ or QECi a contract term and says who certifies it.
- A link between processors from two different manufacturers, even at a scale too small to compute with. DARPA’s HARQ teams are due to finish their 24 months of work in 2028.
This reading would be weakened if a vertically integrated vendor reaches fault tolerance with calibration and module links still closed and buyers accept the trade. IBM’s Starling, planned for 2029, is one scheduled test.
