Riverlane, a British quantum error-correction company, validated a design example for its Quantum Error Correction Interface (QECi) on an Altera Agilex 7 field-programmable gate array (FPGA), the two companies announced on September 10, 2026. A day later, the Dutch control-electronics maker Qblox reported a real-time error-correction loop that it ran with Riverlane over QECi, with a round trip of 6.886 microseconds at the smallest code size tested.
QECi is Riverlane’s specification for the messages that pass between a quantum computer’s control electronics and its decoder, the classical processor that turns the results of repeated error checks into corrections. An FPGA is a chip whose logic circuits can be reconfigured after manufacture.
Qblox and Riverlane ran their loop on real control electronics and a real decoder, but they fed it emulated qubit measurement data and connected no quantum processor.
The Altera validation
Riverlane built the design example for the Agilex 7’s F-Tile transceivers, the circuits that send and receive the chip’s high-speed data. It published the code under a BSD license in QECIPHY, its open-source implementation of the QECi physical layer, which moves raw bits across the link. In the repository’s documentation, Riverlane listed a latency of about 150 to 200 nanoseconds for QECIPHY at a link speed of 12.5 gigabits per second. It reported measured latencies of about 190 to 220 nanoseconds, all on AMD’s Xilinx FPGAs.
Altera said Agilex FPGAs running QECi provide “deterministic low latency” but published no latency figures for the validation. Farhad Shafai, Altera’s vice president of business solutions, said quantum error correction “requires tremendous parallel processing, high-speed connectivity and predictable timing.” Riverlane also joined Altera’s Solutions Acceleration Partner Program.
Riverlane distributes the QECi specification itself through a download form, under terms of use, and watermarks each copy with the recipient’s name and organization.
Altera, based in San Jose, California, has been 51% owned by the investment firm Silver Lake since September 2025, when Silver Lake completed its purchase of that stake from Intel. Intel kept the other 49%.
The Qblox loop
Qblox and Riverlane ran the test under Project SKYTALE, a Horizon Europe project that Riverlane leads. Riverlane received a £2.1 million European Innovation Council Transition grant for the project in 2024, with Qblox as its control-electronics partner.
Qblox’s Cluster control electronics turned the emulated measurement data into syndromes, the error-check results that a decoder reads. The Cluster sent the syndromes over a QECi link to Riverlane’s Deltaflow 2 decoding system and applied the corrections that Deltaflow 2 sent back.
The companies used four sizes of the surface code, an error-correcting code built on a grid of physical qubits. On a quantum processor, the four layouts, at code distances 3, 5, 7, and 9, would require 17, 49, 97, and 161 physical qubits.
A code’s distance is the smallest number of physical errors that can change the stored information without being detected. With a larger distance, the stored information is better protected, but the decoder has more data to process in each cycle.
The companies timed each round trip from syndrome extraction, the readout of the error checks, to the conditional correction that follows. They measured 6.886 microseconds at distance 3, 7.816 at distance 5, 9.866 at distance 7, and 11.886 at distance 9. Qblox included readout integration time, the period spent collecting each qubit’s measurement signal, in those figures.
Qblox wrote that all four configurations met Riverlane’s near-term target of 20 microseconds for the full round trip. Riverlane has described that target as a step toward a goal of 10 microseconds. Qblox attributed 1.114 microseconds of the distance-3 loop and 1.220 microseconds of the distance-9 loop to its own hardware, a difference of 106 nanoseconds.
The companies ran the loop for 50,000 error-correction cycles. Qblox reported a distance-3 round trip of 8.308 microseconds with an earlier Deltaflow 2 release. It published the measurements in a company blog post, not in a peer-reviewed paper.
Altera’s post-quantum secure boot
Two days before the Riverlane announcement, Altera said it had added post-quantum cryptography, algorithms designed to resist attacks by quantum computers, to the secure boot process of its Agilex 3 and Agilex 5 FPGAs. With secure boot, a device loads only configurations it can authenticate. Altera did not name the post-quantum algorithms in its announcement.
Next steps
When it announced the SKYTALE grant in 2024, Riverlane said it would use the project to extend its decoder, running on an FPGA integrated with Qblox’s control system, to support streaming and adaptive decoding during a logical operation. A logical operation is a computation step on qubits protected by error correction. In a March 2026 roadmap, Riverlane described MegaQuOp systems, quantum computers capable of 1 million reliable operations, as “expected before the end of the decade.”
In the same roadmap, Riverlane wrote that in testing, for MegaQuOp computations on superconducting qubits in a regime where leakage is the primary source of errors, its Local Clustering Decoder cut the code distance needed from 33 to 17. Leakage occurs when a qubit escapes the two energy levels used to store its information. Qblox and Riverlane tested codes up to distance 9.
