A company building an error-corrected quantum computer can now buy most of the classical loop that keeps the machine’s qubits corrected. Riverlane sells Deltaflow 2, a decoding system built on field-programmable gate arrays (FPGAs), chips whose logic can be reconfigured after manufacture. NVIDIA sells GPUs and offers NVQLink, an interconnect, along with open-source decoding software. AMD sells CPUs and GPUs that Qblox, a maker of control electronics, has connected to its hardware in latency tests.
The loop begins when control electronics read out a processor’s qubits and turn the readout into syndromes, the results of repeated parity checks that reveal errors without disturbing the stored information. A decoder infers from the syndromes which errors occurred. The control electronics then apply a correction or choose the next operation.
Several companies now sell the classical half of quantum error correction, and in small tests loops using Riverlane’s decoder have met the 10-microsecond reaction time assumed for factoring RSA-2048. On the evidence reviewed here, the number and quality of physical qubits remain a larger gap than the classical loop, although no one has shown real-time decoding across a machine of useful size.
A team of Riverlane and Rigetti researchers closed such a loop on eight physical qubits of a running Rigetti processor. Qblox and Riverlane closed theirs on emulated qubit data. No loop that includes readout and control hardware has been timed beyond distance 9. A code’s distance is the smallest number of physical errors that can change the stored information without being detected.
In its analysis of the control stack, Quantum Observer maps the timescales these parts must span and explains why no portable operating system yet joins them. It also sorts the different jobs that go by the name decoder in a companion explainer.
Who sells which part
Decoders
Riverlane, a British company, describes Deltaflow 2 on its product page as “an FPGA-based QEC system integrating Riverlane’s proprietary hardware decoder” and says it can be configured for different qubit types. The company gives no latency figures on that page. In an April 2026 post, Riverlane set itself a near-term latency target of 20 microseconds and said that utility-scale applications need a latency of 10 microseconds.
Riverlane also writes the interface between its decoder and the control electronics. In its QECi specification, Riverlane defines how the two exchange error-correction data. In September 2026, the company validated a QECi design on an Altera FPGA.
Qblox and Riverlane announced an integrated error-correction offering in March 2026, pairing Qblox control hardware with Deltaflow 2 and Riverlane’s open-source Deltakit software. In the same release, Peter Leek, the founder and chief scientific officer of Oxford Quantum Circuits (OQC), said OQC had integrated Deltaflow into its commercial quantum data center.
In February 2025, Riverlane, IQM, and Zurich Instruments launched a joint project, SurgeonQ, to run lattice surgery with real-time error correction on an IQM superconducting processor with 20 physical qubits. Lattice surgery is a method for operating on logical qubits by merging and splitting the patches of physical qubits that store them. The partners gave no date for results.
On September 29, 2026, Infleqtion and Riverlane signed a memorandum of understanding to evaluate Deltaflow and Deltakit on Infleqtion’s neutral-atom platform, without giving a timeline for the work.
NVIDIA announced a planned investment in Riverlane on October 13, 2026, without disclosing an amount. NVIDIA wrote that Riverlane “has shown how GPUs can accelerate decoder recalibration workflows used in quantum error correction.”
GPUs and the link to them
When NVIDIA introduced NVQLink in October 2025, it listed five control-system builders as supporters: Keysight Technologies, Quantum Machines, Qblox, QubiC, and Zurich Instruments. NVQLink connects a controller to GPU servers over standard Ethernet hardware. In a November 2025 developer post, NVIDIA engineers reported an end-to-end NVQLink latency of 3.84 microseconds on average, with a maximum of 3.96 microseconds over 1,000 samples.
NVIDIA ships its decoding software as CUDA-Q QEC. With version 0.6, released in April 2026, NVIDIA brought GPU decoding into the real-time control loop. In that loop, each syndrome passes from the processor to an FPGA controller and on to a GPU.
NVIDIA included two real-time pipelines in that release. One uses a Relay-BP decoder for quantum low-density parity-check (qLDPC) codes, in which one block of physical qubits stores several logical qubits. In the other, NVIDIA’s Ising neural pre-decoder runs ahead of the open-source PyMatching decoder for the surface code. In a decoder benchmark on the distance-13 surface code at a 0.3% physical error rate, NVIDIA reported 2.1 microseconds of latency per round for the pre-decoder and PyMatching, run on its own Grace CPU and B300 GPU.
Control electronics
Qblox, a Dutch company, sells Cluster control systems. In October 2026, Qblox reported round trips below 4.0 microseconds through NVQLink to an NVIDIA RTX PRO 6000 Blackwell GPU and below 7.2 microseconds to a DGX Spark desktop system. Qblox did not say whether a quantum processor was attached to either setup.
Qblox has also connected its control hardware to AMD processors. On November 12, 2026, Qblox and AMD reported median round trips of 2.70 microseconds to a single AMD EPYC CPU core and 4.05 microseconds to an AMD Instinct MI210 GPU, timed from request to computed reply. Qblox reached the processors through an AMD Alveo V80 card instead of NVQLink. The companies did not say whether a quantum processor was attached.
Quantum Machines, an Israeli company, builds its OPX1000 controller around what it calls a Pulse Processing Unit. On its DGX Quantum page, the company gives a round trip below 4 microseconds between the controller and NVIDIA servers. It wrote that the round trip allows the decoding time budget “to remain below the 10-20 µs limit for useful decoding,” citing a paper by Yaniv Kurman and four other Quantum Machines researchers that the journal Quantum published in July 2026.
In March 2026, Quantum Machines launched what it calls an Open Acceleration Stack, a framework for connecting any classical processor to its control stack, with NVIDIA, AMD, and Riverlane as partners. In September 2026, Quantum Machines demonstrated a CUDA-Q program running end to end on a physical quantum processor over NVQLink, Quantum Computing Report wrote. Quantum Computing Report gave no latency figures and did not name the processor.
Keysight Technologies, another of the five NVQLink supporters, sells a Quantum Control System that it says can “generate, control, and measure quantum signals.”
Zurich Instruments, a Swiss company, launched its ZQCS control system in March 2026. Each shelf has a programmable FPGA and a low-latency link to GPUs and CPUs, according to the company, which put the capacity of a 19-inch rack at more than a thousand channels. Chief executive Andrea Orzati said the company “designed the ZQCS end-to-end for the logical-qubit era.” Zurich Instruments gave no feedback latency for the system in its launch release.
In-house decoders
The largest hardware builders also write their own decoders. In an October 2025 preprint, IBM researchers described an FPGA prototype for IBM’s gross code. Google’s team wrote its own real-time software decoder for a run on a Willow-generation processor with 72 physical qubits. In an August 2026 preprint, IonQ researchers reported a decoder that, running on one laptop processor, kept pace with a simulated trapped-ion machine.
A builder can now assemble the loop from purchased parts instead, as OQC did when it integrated Deltaflow. Riverlane pairs its decoder with Qblox’s control electronics in a commercial offering, works with Zurich Instruments and IQM in the SurgeonQ project, and is a partner in Quantum Machines’ Open Acceleration Stack. All five of NVIDIA’s controller partners support NVQLink.
Latency budgets by qubit type
Designers set the loop’s budget from two numbers, the time one round of parity checks takes and the time a logical operation can wait for a decoded answer. Both vary by qubit type.
| Qubit type | One round of checks | Decoder budget in published work | Source |
|---|---|---|---|
| Superconducting | 1.1 microseconds on Google’s Willow | 10-microsecond control-system reaction time assumed for factoring RSA-2048. Quantum Machines cites a 10–20-microsecond limit for useful decoding | Google, Gidney, Quantum Machines |
| Photonic | Not stated as a round time | Xanadu assigns decoding to its fastest tier, 1 nanosecond to 1 microsecond. Its Aurora system’s FPGA decoder took 64 nanoseconds on a small-scale code, with end-to-end feed-forward slightly below a 1,000-nanosecond budget | Xanadu preprint |
| Trapped ion | 1 to 5 milliseconds assumed in IonQ’s decoder study | Two milliseconds for Quantinuum’s Helios, in NVIDIA’s account. One laptop processor kept pace with a simulated IonQ machine | NVIDIA, IonQ preprint |
| Neutral atom | Milliseconds, according to Google’s Hartmut Neven | No published decoder budget found |
The budgets differ by more than three orders of magnitude, from under a microsecond for photonic decoding to milliseconds for ions and atoms. On a superconducting machine, NVQLink’s average transport time of 3.84 microseconds would use more than a third of a 10-microsecond reaction time before any decoding began. On a trapped-ion machine with a 1-millisecond round, the same transport would take less than 1% of the round.
In a September 2026 preprint, Xanadu’s researchers wrote, “For photonic systems, Tier 1 is a hard requirement for decoding.” Tier 1 is their fastest tier, from 1 nanosecond to 1 microsecond. They placed CPUs and GPUs in a slower tier for backup decoding and assigned the primary decoder of fast-cycling machines to FPGAs and custom chips. They also wrote that a more complex error-correction scheme would lengthen the decoder’s execution time, “potentially exceeding the latency budgets for real-time corrections.”
A supplier’s part therefore suits some qubit types better than others. GPU decoding over Ethernet fits trapped-ion and neutral-atom rounds with time to spare. For superconducting machines, the GPU route leaves about 6 microseconds of the 10-microsecond reaction time assumed in the RSA estimate for decoding, by NVIDIA’s own average transport figure. An FPGA decoder wired into the controller, as in Riverlane’s work with Rigetti, avoids that network hop.
Closed-loop test results
The control-stack analysis lists published loop timings by timescale. Sorted by what was attached to the loop, results of this kind divide into three groups: running processors, emulated qubit data, and setups with no quantum data at all.
| Year | Team | Attached to the loop | Scale | Published timing | Source |
|---|---|---|---|---|---|
| 2024 | Willow-generation processor with 72 physical qubits, running | Surface code, distance 5 | Kept pace with 1.1-microsecond rounds, with a 63-microsecond average latency | Nature | |
| 2024 | Riverlane and Rigetti researchers | Rigetti’s Ankaa-2 superconducting processor, running | Stability experiment on eight physical qubits, also used for a fast-feedback test | Under 1 microsecond per round. A 9.6-microsecond response after nine rounds in the fast-feedback test | Nature Communications, 2026 |
| 2025 | Quantinuum with NVIDIA | Helios processor, running | Bring’s code, eight logical qubits in 30 physical qubits | 67 microseconds, a median decoding time in NVIDIA’s developer post and a reaction time in its release | NVIDIA post, NVIDIA release |
| 2026 | Qblox and Riverlane | Emulated measurements through physical control hardware | Surface code, distances 3 to 9 | 6.886 to 11.886 microseconds from readout to correction | Qblox |
| 2026 | Quantum Machines | Unnamed physical processor | CUDA-Q program over NVQLink | No latency in Quantum Computing Report’s account | Quantum Computing Report |
| 2026 | Qblox with NVIDIA | No quantum processor reported | NVQLink link to GPUs | Under 4.0 microseconds to an RTX PRO 6000 and under 7.2 to a DGX Spark | Qblox |
| 2026 | Qblox with AMD | No quantum processor reported | Serial link to AMD processors | Median round trips of 2.70 microseconds to an EPYC CPU core and 4.05 to an Instinct MI210 GPU | Qblox |
In the published results Quantum Observer found, only the loop by Riverlane and Rigetti researchers closed under 10 microseconds with running qubits. They timed it in a fast-feedback test of nine measurement rounds on their eight-qubit stability experiment, with 6.5 microseconds of decoding and 3.1 microseconds of communication and control latency. Qblox and Riverlane stayed under 10 microseconds through distance 7 on emulated data and went over 10 microseconds at distance 9. A distance-7 surface code would need 97 physical qubits on a real processor.
Quantinuum’s team worked to a slower budget. NVIDIA wrote that the team’s decoder “achieved a reaction time of 67 microseconds, exceeding Helios’ two-millisecond requirement by 32x.” NVIDIA’s developer post gave the same 67 microseconds as a median decoding time.
Researchers have also timed decoders on their own, without readout and control hardware, at larger distances. NVIDIA’s distance-13 figure is one such benchmark. In a December 2025 preprint, Google DeepMind researchers reported a neural decoder that they said could decode the surface code in real time up to distance 11, timed on simulated data. In an August 2026 preprint, researchers at China’s National University of Defense Technology reported decoding at 1 microsecond per round up to distance 19 with THQLink, a system in which an FPGA emulated the control electronics.
Qblox split two of the timings, at distances 3 and 9, between its own hardware and everything else in the loop. The company attributed 1.114 microseconds of the distance-3 loop and 1.220 microseconds of the distance-9 loop to its own equipment. Over the same range, the full loop grew by 5.0 microseconds, of which about 4.9 occurred outside Qblox’s equipment.
In their March release, Qblox and Riverlane described Deltaflow 2 as “directly integrated with Qblox’s control architecture to enable sub-microsecond feedback between detection and correction.” In the September tests, Qblox timed the full loop, from syndrome extraction to correction and including readout integration, at 6.886 microseconds or more.
None of the timed loops in the table operated on two code patches at once, the step that lattice surgery requires. The SurgeonQ partners set out to run that step on IQM hardware. In the preprint version of their paper, the Riverlane and Rigetti researchers wrote that the throughput and latency of their decoder, together with improvements to the device, should enable lattice surgery and the teleportation of magic states, prepared resources that a fault-tolerant machine consumes for each gate its code cannot apply directly.
Riverlane wrote in April 2026 that Deltaflow 3 would launch later that year and focus on fast logical gates by lattice surgery. As of November 2026, the company’s Deltaflow page did not list it.
The companies that built the parts or ran the experiments produced every figure in the table. Alongside the Q Competition in its Quantum Genesis initiative, the Department of Energy (DOE) has asked national laboratories to propose a validation testbed that would characterize each layer of a quantum computer, classical control systems included.
The quantum side of the gap
Craig Gidney of Google Quantum AI estimated in a 2025 preprint that a 2048-bit RSA key could be factored in less than a week by a machine with “less than a million noisy qubits.” He assumed the 10-microsecond reaction time, a uniform gate error rate of 0.1%, and a surface-code cycle of 1 microsecond.
Google’s Willow has 105 physical qubits, and Quantinuum’s Helios has 98, according to Quantum Observer’s report on the Sandia-led benchmark. Gidney’s machine could have up to a million physical qubits, about 9,500 times as many as Willow, with a gate error rate of 0.1% across all of them.
A Sandia-led team reported in a September 2026 preprint that “current QUOPS scores are insufficient by roughly five orders of magnitude” for factoring RSA-2048 or estimating an energy level of the FeMoco molecule. QUOPS is a benchmark for comparing quantum computers built on different hardware. Fitting capability data back to 2018 and extending the trend, the team estimated that machines would not reach such problems until 2050–2070. It also calculated that progress would have to run about four times faster to meet the early-2030s dates that hardware roadmaps set for major scientific capability.
IBM wrote on November 5, 2026, that its experiments had demonstrated “up to 70 logical qubits and 438 hard operations,” without saying whether one experiment reached both. DOE defines a hard operation as one that is difficult in a machine’s error-correction scheme but necessary for universal computation.
Riverlane has put a number on the code distance that useful machines need. In March 2026, the company wrote that, in testing, its Local Clustering Decoder halved the code distance needed for MegaQuOp computations, runs of a million reliable operations, from 33 to 17. In a footnote, Riverlane limited the result to superconducting qubits in which leakage, a qubit’s escape from the two states that store information, is the main source of errors.
On a rough comparison across different tests, decoder makers still have a factor of two to three in code distance to cover, on running hardware, beyond the distance-7 loop that Qblox and Riverlane closed under 10 microseconds on emulated data. A machine with hundreds of logical qubits would also need its loop to keep pace on every code patch at once. Of the teams cited here, only IonQ’s researchers have decoded at that scale, for a simulated machine of up to 408 logical qubits.
The case that the loop is still the constraint
Qblox’s chief executive, Niels Bultink, put the loop’s importance this way in October 2026. “Quantum computers will scale only as fast as the classical control systems around them,” he said.
Qblox and Riverlane measured a loop that grew by 5 microseconds between distances 3 and 9 and crossed the 10-microsecond budget well before distance 17, the figure Riverlane gives for MegaQuOp computations on leakage-dominated superconducting qubits. None of the timed loops handled lattice surgery either, which requires decoding two patches together while they are merged.
Independent measurement is also missing on the decoding side. Every timing cited above was published by the vendor or research team that did the work.
Those are engineering risks on chips that other industries buy in volume. At least seven companies now sell parts of the loop. Five of them – Riverlane, NVIDIA, AMD, Qblox, and Quantum Machines – have published the latency figures cited here.
On the quantum side, Gidney allowed for about 9,500 times as many physical qubits as Willow has. On the Sandia team’s trend line, machines of that capability are decades away without faster progress. The qubit ratio and the code-distance ratio come from different models and workloads, so they indicate scale without ranking the two gaps.
The size of the qubit gap also depends on decoder accuracy. If Riverlane confirms its halving of code distance on running hardware, a superconducting machine with leakage as its main source of errors would need 75% fewer physical qubits for the same logical qubits, by the company’s own estimate. Decoder makers may therefore do more for fault tolerance through accuracy than through speed.
What would confirm or overturn this
Four developments would confirm or overturn this reading. Each would appear first in a company release, a preprint, or a government report.
- A loop on a running processor at distance 9 or above, closed inside 10 microseconds and published with its latency distribution. SurgeonQ’s lattice-surgery work on IQM hardware is one candidate.
- Independent timings of commercial loops from the national laboratories that DOE selects for its validation testbed.
- Deliveries against dated targets. DOE plans its final evaluation of first-generation fault-tolerant machines in September 2028. IBM has scheduled Starling, a machine of 200 logical qubits, for 2029. A builder that reaches either target with a purchased decoding loop would show that the classical half has become a product.
- A jump in qubit counts that outruns the decoders. If error-correction experiments on thousands of physical qubits at error rates near 0.1% appear while loops at distances in the teens still miss the 10-microsecond budget, the classical loop would become the binding constraint again.
Until one of these appears, a buyer can source the classical loop from several suppliers and should still expect a fault-tolerant machine’s schedule to depend on how fast its builder can add physical qubits at low error rates.
