IonQ said on September 22, 2026, that its researchers had run a real-time decoder for a simulated fault-tolerant trapped-ion quantum computer with up to 408 logical qubits on a single standard processor. A logical qubit is one unit of quantum information spread across many physical qubits so that errors can be found and corrected. A decoder is the classical software that turns error-check results into corrections.
The researchers used a 2024 Apple M4 Max processor in a MacBook Pro, according to a preprint by IonQ’s Min Ye, Andrii Maksymov, and Nicolas Delfosse. The preprint, posted to arXiv on August 25 and revised on September 3, has not been peer reviewed.
IonQ’s researchers showed that one laptop processor could keep pace with the decoding for their trapped-ion design, but they generated every syndrome, the error-check data a decoder reads, in a noise simulation and used no quantum hardware. IonQ described the software in its announcement as the industry’s first end-to-end real-time quantum error correction decoder to run on a single standard CPU.
How decoding works
A fault-tolerant quantum computer runs repeated cycles of parity checks on groups of its physical qubits. Each check can flag an error without disturbing the quantum information the qubits store.
The decoder reads the results and works out which errors occurred. The authors wrote that the decoder must keep pace “to avoid a decoding backlog that can induce an exponential slowdown of the quantum computation.”
The workloads
The team tested three workloads compiled for Walking Cat, the fault-tolerant trapped-ion architecture that IonQ researchers described in an April preprint. Walking Cat uses quantum low-density parity-check codes, a family of error-correcting codes in which each parity check involves only a few qubits.
The largest configuration had 68 memory blocks storing six logical qubits each and 20 magic-state factories, built from 11,680 physical qubits. A magic-state factory prepares the resource states that a fault-tolerant computer consumes to perform T gates, operations a machine needs to run arbitrary quantum algorithms.
One workload was a 40-layer random circuit of the kind physicists use to study measurement-induced phase transitions, abrupt changes in how much entanglement builds up as qubits are measured more often. After compilation, it occupied 102 logical qubits and needed more than a million T gates. The other two were single time steps of a simulated Heisenberg model, a standard description of interacting magnetic spins, with 64 sites on 102 logical qubits and 266 sites on all 408.
Results
The authors measured the cost of decoding delays as stretch: the number of extra error-correction cycles caused by late decoding, divided by the number of cycles needed with an instantaneous decoder. They assumed a cycle of 1 millisecond for the two 102-logical-qubit workloads, a timescale they called long-term for trapped-ion hardware. For the largest workload, they assumed 5 milliseconds, a timescale they called near-term.
At a simulated two-qubit gate error rate of 1 in 10,000, the authors measured stretch of 0.24% for the random circuit, 0.18% for the 64-site model, and 0.02% for the 266-site model. At 5 in 10,000, the highest rate tested, the figures were 11.53%, 10.25%, and 0.72%. The authors wrote that error rates in the tested range have been achieved on small trapped-ion devices.
The error decoders kept the record of corrections for the whole computation and ran on eight of the processor’s 16 cores. Faster, less accurate outcome decoders ran on four more cores and had until the next cycle boundary to return each logical measurement result. The authors counted the time spent building the decoder’s model of likely errors during the run, as well as delays from decoding processes competing for memory.
Claims and limits
In its release, IonQ said its benchmark circuits, simulating up to 408 logical qubits across 88 memory blocks, were executing “more than 31.5 million individual quantum operations.” In the paper’s first table, the authors listed 31,548,792 syndrome-extraction cycles for the largest workload, summed across all 88 code blocks. Each such cycle is one round of parity checks on one block.
Other teams have run real-time decoders on quantum hardware. In 2021, Honeywell researchers reported using one, a lookup-table decoder, in error-correction experiments on a trapped-ion computer with 10 physical qubits.
IonQ also said the decoder added as little as 0.02% stretch under standard operational noise. The authors obtained that value for the 408-logical-qubit workload at the lowest simulated error rate, with the 5-millisecond cycle. At the same error rate with the 1-millisecond cycle, they measured 0.18% and 0.24% for the other two workloads.
The authors did not simulate in full the factory that prepares cat states, a kind of entangled state that a Walking Cat machine consumes to perform logical operations. According to the authors, the decoder has no role in that factory.
In each magic-state factory, the authors replaced the physical magic state fed into it with a simpler stabilizer state, one that a classical computer can simulate efficiently. They wrote that they set out to benchmark the decoding workload, not the factories’ output fidelity.
The team also simulated its compiler and logical-control layer but excluded that work from the timings. The authors reported decoding speed but no logical error rates for the three workloads.
Roadmap
IonQ said the result validated “a core pillar” of Walking Cat. The company launched its Superion 256 platform on September 8 and plans to deliver it to customers in 2027. It called the follow-on model, Superion 10K, “the first hardware generation built to run IonQ’s Walking Cat architecture.”
In that release, Chris Ballance, IonQ’s president of quantum computing, said, “CMOS integration is expected to reach full fault tolerance reality in a 2027 lab setting at IonQ, and manufacturable, commercial reality in 2028.” IonQ said Superion 10K integrates CMOS, the transistor technology of conventional computer chips, onto the chip.
