IBM Research reported on October 13, 2026, that teams of AI coding agents had optimized the hardware design of a quantum error-correction decoder, the classical circuit that reads a quantum computer’s error checks and works out which errors occurred. Agents built on GLM-5.3, an open-weight model from the Chinese developer Z.ai, cut the design’s estimated latency 52-fold for about $26 in model inference on IBM’s own GPUs.
When the researchers used Anthropic’s Claude Opus 5 in every role, the agents found a design 204 times faster than the original, at an estimated inference cost of about $299. The researchers reported both figures in a paper that IBM posted with its announcement.
The speedups are estimates from a high-level synthesis tool, not measurements of a decoder running on hardware. Such a tool converts a program into a chip design and estimates how fast the design would run. The authors ran each configuration once and wrote that the results reflect those particular searches, not fixed properties of the models.
The test case
The seven-person team, with Abhishek Bhandwaldar and Ruchir Puri as corresponding authors, chose a decoder for the gross code, an error-correcting code that IBM researchers described in Nature in 2024. The decoder implements Relay-BP, an algorithm IBM published in June 2025 for the quantum low-density parity-check codes on which the company has built its fault-tolerance roadmap.
A coordinator agent planned the search and assigned optimization ideas to four worker agents, in a setup IBM calls an agent factory. After each worker rewrote the decoder’s C++ code, a verifier checked the new code for correctness.
The team synthesized every candidate with AMD’s Vitis high-level synthesis tool for an AMD field-programmable gate array (FPGA). Over five rounds of 20 ideas, the coordinator used the synthesis results to choose each next round.
Puri, an IBM Fellow and chief scientist of IBM Research, described hardware optimization under this approach as “a coordinated cycle of exploration.”
Results by configuration
The unmodified design had an estimated latency of 28,231 microseconds. Under the same budget of 100 ideas, the researchers reported these best estimates for the three configurations:
- Claude Opus 5 as coordinator and workers: 139 microseconds, a 204-fold speedup, for $299.45 in inference.
- An Opus coordinator directing GLM-5.3 workers: 223 microseconds, 126-fold, for $105.25.
- GLM-5.3 in both roles: 545 microseconds, 52-fold, for $25.95.
IBM priced the GLM-5.3 tokens at $0.1077 per million, its estimated cost of serving them on 544 NVIDIA H100 GPUs that it also uses for other workloads. The team priced Opus tokens at Anthropic’s standard API rates. IBM said the costs cover model inference only and exclude the other stages of hardware development.
When the researchers doubled the budget for the GLM-5.3-only configuration to 200 ideas, the agents’ best design had an estimated latency of 468 microseconds, a 60-fold speedup. The agents reached most of that speedup within the first 100 ideas. IBM said in its blog that the GLM-5.3-only agents also produced the optimized design with the smallest hardware area.
In an appendix, the authors gave an agent a decoder architecture that IBM researchers published in 2025, with its C implementation and test bench, and had it write register-transfer-level code, the lower-level hardware description. The agent’s version decoded 1,000 test cases in about 30,000 clock cycles, matching IBM’s hand-written design. It used about 80% more lookup tables, the chip’s basic logic elements, and ran at a slower clock.
Next steps
The team plans to test adaptive search budgets and selective use of stronger models, and to compare configurations at equal total spending on inference, synthesis, and verification. IBM’s roadmap depends on decoders fast enough to keep pace with its hardware. The company has said that Starling, a fault-tolerant system with 200 logical qubits that it plans to deliver by 2029, must decode measurements from its logical qubits in real time.
