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One block of Infleqtion's code stores 18 logical qubits in 98 physical data qubits. Infleqtion's Victory Omole wrote that those numbers are "not a hardware resource estimate." The company has not run the code on hardware.
Xanadu researchers timed round trips of 16-byte messages between an AMD FPGA board and an AMD Threadripper CPU at a median 2.305 microseconds, first as a plain echo and then with a small lookup-table decoder. No quantum processor was attached.
Qblox and Riverlane timed the full round trip from error check to correction on commercial hardware at 6.886 to 11.886 microseconds. They emulated the qubit signals and connected no quantum processor.
QuEra sells neutral-atom machines with 256 and 260 physical qubits, while Harvard and MIT teams that include its co-founders have run arrays of more than 3,000 atoms. Its Libra computer, due in 2028, is the test.
A Sandia-led team scored Google, IBM, and Quantinuum processors and a logical-qubit machine on one scale. Helios-1 led at 1,504 without discarded runs, against about 250 million that the authors calculated for factoring RSA-2048.
Quantinuum's team encoded two logical qubits in 20 physical data qubits on its Helios machine and beat unencoded baselines without discarding runs. The team decoded errors after the runs and ran no non-Clifford gates.
Error-correction, key-distribution, and algorithmic decoders are three of several jobs that share one name. Only the first runs against a machine's clock, where its speed and accuracy affect the clock rate and qubit cost of fault-tolerant designs.
Five physicists calculated that an Andreev qubit in a superposition should produce an oscillating supercurrent with no applied voltage. In simulations described in their preprint, they read one test state from that current with infidelities of 0.15% to 0.48%.
In a preprint, Qarakal's researchers counted the physical qubits for one merge operation and reached the tenfold ratio by extrapolating beyond the code distances they simulated. The company has not reported a Pangaea chip.
About 0.5% of gates ended in a detected erasure and at most 0.12% in an undetected error. The authors projected the error-correction advantage from simulations, assuming perfect erasure checks and leaving out measurement errors.
