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Google and MIT researchers spread error-correcting codes across small chip modules, with 42 to 116 physical qubits in their main examples. They have not tested the design on hardware or estimated what a complete algorithm would cost on it.
The Delft team tested its leakage reduction unit in error-correction experiments on five and seven physical qubits, with no runs discarded. The authors wrote that further research is required at larger code distances and for other codes.
Riverlane, NVIDIA, and several control-electronics makers now sell parts of the loop that turns error checks into corrections. Among the superconducting tests surveyed, loops using Riverlane's decoder have met a 10-microsecond budget, in small configurations only.
The code Infleqtion used is guaranteed to flag any single error but not to correct one, apart from the loss of an atom. A full paper with methods, resource counts, and statistics is still to come.
Microsoft and Qolab researchers would call a logical qubit scalable only if a machine sustains it with repeated error correction and decodes errors in real time. DOE plans to pay for logical qubits under counting methods negotiated with each company.
IonQ researchers ran a real-time decoder on 12 cores of an Apple M4 Max and measured decoding delays that lengthened simulated run times by 0.02% to 11.53%. They generated all error-check data in a noise simulation, without quantum hardware.
The team restored error suppression in a stand-in test for logic gates by removing defective parts. The larger distance-5 code beat a distance-3 code only after the team discarded runs affected by leakage, and only in one basis.
Companies that demonstrate a first-generation machine at an evaluation planned for September 2028 would split a $100 million pool. Only $2.5 million of the planned total is fiscal 2026 money.
The parallel gate took 14.8 microseconds and had an estimated fidelity of 0.92. The authors wrote that errors in preparing and reading out the qubits still limit the entangled states they can make.
Researchers lengthened a surface code in one direction on IBM Heron processors and reduced the matching type of logical error. With a measure that combined both error types, the team found no subthreshold scaling on its best-performing chip.
