Xanadu Quantum Technologies and AMD said on September 10, 2026, that they had launched Backline, an open-source feature suite for Xanadu’s PennyLane software that connects quantum processors with CPUs, GPUs, and field-programmable gate arrays (FPGAs). The companies said Backline achieves “end-to-end classical-quantum loop times under 3 microseconds.” They also said standard AMD EPYC or Threadripper processors “can handle low-latency demands out of the box,” without enterprise GPUs.
PennyLane is Xanadu’s software for programming quantum computers. An FPGA is a chip whose logic circuits can be reconfigured after manufacture. In quantum error correction (QEC), a classical decoder must turn the results of repeated error checks into corrections fast enough to keep pace with the quantum hardware.
Xanadu’s researchers measured the sub-3-microsecond loop between an FPGA and a CPU that echoed test messages back, with no quantum processor attached. In their preprint, they assigned the main error-correction decoder for fast-cycling photonic and superconducting machines to FPGAs and custom chips. They placed their measured CPU and GPU paths in the range for backup decoding. AMD described the tests as internal benchmarks to determine the latency floor.
The measurements
All 13 authors of the preprint, submitted on September 8 and not peer reviewed, are Xanadu researchers. They reported median round trips of 2.305 microseconds between an AMD VPK120 FPGA board and an AMD Ryzen Threadripper PRO CPU, and 4.5 microseconds to an AMD Instinct MI210 GPU. Only the CPU path had a median under 3 microseconds.
The FPGA acted as the controller, the role a quantum computer’s control electronics would play. It sent each 16-byte message, including an 8-byte syndrome, over RDMA over Converged Ethernet version 2 (RoCE v2), a protocol that lets one device write directly into another’s memory across a network. A syndrome is the error-check data that a decoder reads.
In this test, the CPU and GPU “return the received value without decoding,” the authors wrote. Over 999,999 round trips per path, they recorded maximums of 2.590 microseconds on the CPU path and 5.285 microseconds on the GPU path. In the paper’s example programs, the authors used null.qubit, a PennyLane placeholder device that performs no quantum computation.
In the same setup, the researchers ran a lookup-table decoder for the Steane code on the CPU path. The Steane code stores one logical qubit, an error-protected unit of quantum information, in seven physical qubits. The decoder, which reads each correction from a precomputed table, took a median 2.305 microseconds, the same as the echo.
On the GPU path, a decoder using belief propagation with ordered-statistics decoding (BP-OSD) took a median 31.075 microseconds for a code that stores one logical qubit in 13 physical qubits. The authors called that BP-OSD decoder “a naive implementation” and listed possible optimizations.
The timing tiers
The authors divided real-time work, computing that must meet fixed deadlines, into tiers. “ASICs, FPGAs, and embedded real-time coprocessor cores are the primary targets at this scale,” they wrote of the fastest tier, Tier 1, from about 1 nanosecond to 1 microsecond. ASICs are custom chips built for a single task.
They named the next tier, from about 1 to 100 microseconds, the synchronous co-processing tier. They described it as a soft real-time regime “for supportive, high-importance tasks such as backup decoding and auxiliary processing.” In soft real-time work, an occasional missed deadline is tolerable.
Xanadu builds photonic quantum computers, in which qubits are encoded in particles of light. “For photonic systems, Tier 1 is a hard requirement for decoding,” the authors wrote. They also wrote that Xanadu’s Aurora system ran its error-correction decoder on an FPGA with a latency of 64 nanoseconds.
The authors wrote that an enterprise-grade GPU “is not necessarily a prerequisite for real-time QEC.”
Availability
Backline is available as an open-source feature suite within PennyLane, the companies said. Xanadu published the paper’s demonstrations and benchmarks in a GitHub repository under the Apache 2.0 license. The core Backline code is part of PennyLane and of Catalyst, PennyLane’s compiler.
Christian Weedbrook, Xanadu’s founder and chief executive, said the work with AMD “shows that AMD’s hardware can handle these demanding latency budgets right now, even with standard CPUs.” AMD co-designed Backline with Xanadu so that “a single Python program can span AMD EPYC and Threadripper CPUs, AMD Instinct GPUs, AMD Versal FPGAs and AMD Pensando networking,” said Scott Tease, AMD’s corporate vice president of HPC and Sovereign AI.
The researchers have reported no round-trip times with a quantum processor attached. On the CPU path, they decoded only the seven-qubit Steane code.
