Researchers at D-Wave Quantum described a two-qubit gate for dual-rail erasure qubits, a superconducting design built so that most errors can be detected, in a Nature paper published on August 5, 2026. The authors reported a gate time of about 500 nanoseconds, a detected-error rate of about 0.5% per gate, and an undetected error of at most 0.12% per gate.
D-Wave bought Quantum Circuits Inc., the New Haven, Connecticut, company where the research began, in January for $550 million in stock and cash. Nature received the manuscript on May 6, 2025, about seven weeks after the team posted a preprint. Robert Schoelkopf, a Yale physicist who co-invented the transmon qubit and is now D-Wave’s chief scientist, is the senior author.
The team built two dual-rail qubits and ran no error-correcting code across them, so it projected the error-correction advantage from simulations with a deliberately simple noise model.
How a dual-rail erasure qubit works
In a dual-rail qubit, the value 0 or 1 is encoded in which of two superconducting cavities contains a single microwave photon. If the photon is lost, both cavities end up empty, a detectable state that physicists call an erasure.
“In general, a code that corrects up to n bit flips can correct up to 2n erasures,” three of the authors, Kevin Chou, James Teoh, and Nitish Mehta, wrote in a D-Wave blog post.
The device used four three-dimensional coaxial cavities, two for each qubit, along with three couplers and an extra circuit for each cavity. All seven of those circuits are transmons, the type that most superconducting quantum computers use as qubits.
The middle coupler performed a controlled-Z, or CZ, gate, an operation that flips the sign of the joint state when both qubits are 1. In what the authors call a Swap-Wait-Swap gate, a photon moves from a cavity into the coupler, the qubits interact for a set time, and the photon moves back. If a qubit has already lost its photon, the gate does not occur, a property the authors verified experimentally.
What the team measured
After discarding runs with a detected erasure, a step called post-selection, the team measured an end-to-end state fidelity of 99.60% for a single CZ gate. That figure includes errors from preparing and measuring the qubits, from single-qubit gates, and from the CZ gate itself. Detected erasures occurred in 0.53% of gates, about four times as often on the control qubit as on the target.
With post-selection, the authors put a conservative bound of 0.12% per gate on the remaining error, using sequences of up to 103 repeated gates, according to the accepted manuscript that D-Wave posted. With interleaved randomized benchmarking, a standard method of comparing random gate sequences with and without the gate of interest, they measured 0.108% error per gate.
Bit flips, in which the photon switches cavities, were bounded at a few parts per million per gate. Beyond about 15 repeated gates, fidelity declined roughly quadratically. The authors suggested calibration drift or fluctuations in the coupler’s frequency as possible causes and said the root cause needs further investigation.
D-Wave’s claims and the paper
D-Wave cited “approximately 99.9% fidelity during two-qubit operations” in its press release and did not give the erasure rate there. The authors’ blog post the same day put that rate at about 0.5%. The authors obtained their error figures near 0.1% by post-selection, excluding runs in which an erasure was detected.
D-Wave said its roadmap target for Lambda, or Λ, is 10. Lambda is the factor by which the logical error rate falls each time the code distance, a measure of how many errors a code can correct, increases by two. The authors ran no error-correcting code on hardware, so they reported no measured Λ.
Using Stim, an open-source simulator, the authors modeled surface-code memory, a standard error-correction test, with their measured gate errors and obtained Λ ≈ 27. For comparison, they obtained Λ ≈ 14 for a gate with a 0.1% depolarizing error rate, a model in which every type of error is equally likely. The authors described that rate as state of the art for two-qubit gates with “unstructured” errors.
The authors treated erasure checks as perfect in their simulations and wrote that the noise models were “chosen to be simplistic.” More realistic simulations must also include errors from single-qubit gates, from all measurements including erasure checks, and from idling, “which reduce the value of Λ,” the authors wrote. In their conclusion, they wrote that the results “provide a path to realize large error correction gains of 10 or more with an increase in code distance in the near future.”
Schoelkopf said in the release that the gate is already integrated into D-Wave’s gate-model systems, “where it is delivering comparable performance.” D-Wave named no systems in the release and gave no data for them.
The authors declared that those affiliated with D-Wave have a financial interest in the company and that seven of them, including Schoelkopf, have filed a provisional patent on the gate.
Next steps
The authors wrote that fuller simulation results will appear in a separate paper on error-correction scaling in a dual-rail cavity surface code. D-Wave said in January that it planned an initial dual-rail system for general availability in 2026. D-Wave has set 2032 as the target for a 100-logical-qubit system that can perform more than 1 million operations.
