In a March 2026 preprint, 13 IBM researchers set out a reference architecture for joining quantum processors to supercomputers and drew its main software boundary around time. Error-correction decoding runs “within ~10 μs control loops” on custom electronics, behind a Quantum System API that the authors called “the sole programmatic boundary” around the real-time layer. Error data for a second, outer code arrives “typically ~100 μs to 1 ms” and goes to nearby GPUs or other accelerators, with the Slurm job scheduler above them.
Xanadu’s software team drew the same lines six months later. In a September preprint on Backline, a compilation framework that Xanadu launched with AMD, the team sorted quantum-classical work into four tiers by deadline. They run from a real-time tier of 1 nanosecond to 1 microsecond up to a distributed tier of more than 1 second.
Quantum computing has no widely adopted operating-system layer that makes fault-tolerant hardware interchangeable across vendors. The layers it would have to join run on clocks from nanoseconds to hours, and no published interface carries state across that range. Existing systems offer narrower portability, including QNodeOS for network nodes, and although vendors have written software for every layer, a buyer still cannot swap one company’s processor, control electronics or decoder for another’s by recompiling instead of rewriting.
In a conventional computer, the kernel is the core of the operating system. It allocates processors, memory and devices among programs and hides each device’s details behind a driver. A quantum kernel would do the same for qubits, error correction, calibration and scheduling.
Software in every layer
The vendors that build whole machines ship their own stacks. IBM’s Quantum Compute Service (formerly Qiskit Runtime) runs jobs on IBM processors in three modes. In one of them, a user has exclusive use of a machine.
Quantinuum launched its Helios computer in November 2025 with “a completely new stack” and a new programming language, the company wrote. Origin Quantum in Hefei opened its Origin Pilot operating system for download in February 2026, Chinese state media reported. Quantum Observer covered the Origin Pilot release in March.
Among independent companies that sell single layers, Q-CTRL offers Fire Opal. According to the company’s documentation, the software applies “AI-driven error suppression” to circuits on IBM’s cloud processors and on IonQ machines through Amazon Braket. In May 2025, Quantum Machines released QUAlibrate, an open-source framework that represents calibration as a graph of reusable components. The company said that a multi-qubit calibration at the Israeli Quantum Computing Center took 140 seconds.
Riverlane publishes QECi, a specification for the link between control electronics and a decoder, the classical processor that turns error-check results into corrections. In September, Quantum Observer reported that Altera had validated a QECi design example on an Agilex 7 FPGA, a reconfigurable chip. Qblox separately tested its control electronics over the link with Riverlane’s Deltaflow 2 decoder.
NVIDIA introduced NVQLink in October 2025 to connect quantum control hardware to GPU supercomputers. The company said NVQLink supported 17 quantum-processor builders and five control-system makers.
Haiqu and qBraid, neither of which builds quantum computers, also applied the label “operating system” to new products in 2026. In May, Haiqu launched what it called an “agentic quantum operating system,” built around an “Agentic Intelligence” layer that “automates application design,” a software kit for data loading and error mitigation, and a runtime that orchestrates applications. In October, qBraid announced qBraid OS as software that hardware operators can use to manage accounts, queues and billing. It opened the product “to early-access partners,” according to its product page.
The strongest case that a kernel already exists
The best evidence for a portable layer is in four places. Origin Quantum and a provincial research center directed by its chief scientist described Origin Pilot as compatible with superconducting, trapped-ion and neutral-atom processors. “Users can quickly integrate with quantum chips of multiple physical types,” Dou Menghan, who leads its development team, told the Global Times. The research center also told the newspaper that the system supports parallel execution of quantum tasks and automatic qubit calibration.
The Science and Technology Daily, the Global Times and Xinhua all covered the release. None of them reported a test on another company’s hardware or any performance figures.
qBraid said its system can “connect through the processor’s existing interface, or directly to the system’s control electronics.” In its October announcement, the company said qBraid OS is “designed to use NVIDIA CUDA-Q for quantum error-correction decoding.” On its product page, qBraid names no supported devices for qBraid OS and does not mention calibration or pulse control. Through its existing platform, the company gives access to systems from 18 hardware providers.
The strongest case is QNodeOS, an operating system for quantum network nodes that a team led by Stephanie Wehner at Delft University of Technology published in Nature in March 2025. “The QDriver is the only hardware-dependent element of the architecture,” the authors wrote. They ran the full system on two nodes built from nitrogen-vacancy centers in diamond. Separately, they validated a QDriver for one trapped calcium ion with single-qubit gates.
The authors wrote that their architecture can execute programs on any quantum processor platform that fits their system model. By their account, porting it to a new platform would mean rewriting one component, the QDriver.
QNodeOS exchanges messages with its hardware at 100 kHz in the nitrogen-vacancy version and 50 kHz in the trapped-ion version, one message every 10 to 20 microseconds. Google’s Willow processor finishes a round of error-correction checks every 1.1 microseconds. The two figures measure different boundaries, a host-to-device message interval and an internal check cycle, and QNodeOS has not been tested on a superconducting error-correction workload.
In Colorado, a regional technology hub and five partner companies declared their multi-vendor Q-PAC system operational in March 2026. They built it from a QuantWare processor, Qblox control electronics, Maybell cryogenics and Q-CTRL software under a shared reference design. They released no gate error rates, benchmark results or coherence times, the spans over which the qubits keep their quantum information.
Designers divide the stack by timescale
In 2021, Riverlane described a hardware abstraction layer, built with a UK consortium under a £7.6 million government grant, as “the first universal quantum API.” Riverlane archived the project’s code repository in March 2022, marked it as deprecated and noted that it had moved to the UK’s National Physical Laboratory (NPL). In a 2023 paper on the design, seven Riverlane and four NPL authors defined three levels of access by latency.
At the lowest level, latency stays below the qubits’ decoherence time, another term for coherence time. At the middle level it is “comparable with the qubit decoherence time,” and at the top it is “typically larger than the qubit decoherence time.”
The authors’ core commands included single-qubit operations and control commands for photonic, silicon, superconducting and trapped-ion platforms. At the top level, they added one two-qubit gate, the CNOT, to the core commands. They left native two-qubit gates at the two lower levels as platform-specific options.
IBM and Xanadu drew the same kind of map in 2026. Below are published examples of the clocks involved, from the fastest to the slowest.
| Time scale | What happens | Published example | Source |
|---|---|---|---|
| about 10 nanoseconds | a control pulse rotates one superconducting qubit | 7.9-nanosecond gate with an error of 1.56×10⁻⁴ | IQM researchers, 2024 |
| under 0.5 microseconds | real-time decoding of IBM’s qLDPC codes | under 480 nanoseconds | IBM, 2025 |
| about 1 microsecond | one round of error-correction checks | 1.1 microseconds on Willow | Google, 2024 |
| about 10 microseconds | control-system reaction time assumed for factoring RSA-2048 | 10 microseconds | Gidney, 2025 |
| 16 to 63 microseconds | real-time decoding of Willow’s distance-5 data | 63-microsecond average with Google’s decoder, 16.32-microsecond mean with Riverlane’s on the same data | Google, 2024, Riverlane, 2026 |
| 100 microseconds to 1 millisecond | outer-code decoding on GPUs | IBM design parameter | IBM, 2026 |
| 1 to 5 milliseconds | error-correction cycle assumed for trapped ions | IonQ decoder study | IonQ, 2026 |
| tens of milliseconds | a superconducting qubit’s relaxation time changes | switches of nearly 10-fold | Berritta and co-authors, 2025 |
| about 1 hour | correlated bursts of errors | about once an hour in repetition-code runs on Willow | Google, 2024 |
| about 1 day | routine calibration | “about once a day” on IBM processors | IBM documentation |
A 7.9-nanosecond pulse and a daily calibration are about 13 orders of magnitude apart. The top of Xanadu’s real-time tier, 1 microsecond, and the bottom of its distributed tier, 1 second, are six orders of magnitude apart.
Nanosecond control and three kinds of physics
At the bottom of the stack, a hardware abstraction has to hide differences in physics. Researchers at IQM, a Finnish hardware maker, reported 7.9-nanosecond single-qubit gates on superconducting qubits, driven by shaped microwave pulses. Quantinuum’s Helios moves charged barium atoms from storage rings to logic zones through an ion junction that the company compares to “a traffic intersection for qubits.”
Neutral-atom machines hold atoms in beams of laser light called optical tweezers. In a paper published in Nature in 2025, Caltech physicists reported that they had trapped more than 6,100 atoms this way and shown “coherence-preserving qubit transport.”
The authors of OpenQASM 3, an open language for quantum circuits and their control pulses, fixed pulse timing at compile time. A gate’s pulse definition “must have a definite duration known at compile time,” according to the language specification. Every branch of conditional logic inside such a definition must have the same duration. Decisions that depend on measurements made during the run are left to the real-time control hardware.
The microsecond decoder deadline
Error correction has the hardest deadline in the stack. IonQ researchers wrote in an August preprint that the decoder must keep pace “to avoid a decoding backlog that can induce an exponential slowdown of the quantum computation.”
Google’s real-time decoder kept pace with Willow’s 1.1-microsecond cycle for up to a million cycles, with an average latency of 63 microseconds at distance 5. Code distance is the smallest number of physical errors that can change the stored information without being detected. In April 2026, Riverlane reported a mean latency of 16.32 microseconds for its Deltaflow 2 decoder on the same distance-5 data, replayed through an emulator. Riverlane wrote that the comparison “should not be interpreted as strictly like-for-like.”
In his 2025 estimate for factoring a 2048-bit RSA key, Craig Gidney of Google Quantum AI assumed “a control system reaction time of 10 microseconds,” about a sixth of the average decoder latency Google reported for Willow.
Riverlane engineers designed a custom decoder chip that “occupies 0.06 mm² and consumes only 8 mW of power,” for surface codes of up to 1,057 physical qubits. IBM said in November 2025 that it had decoded its qLDPC codes, which store many logical qubits in one block of physical qubits, in real time in “less than 480 nanoseconds.”
IBM researchers wrote on November 11, 2026, that the company is building a decoder chip on 2-nanometer technology for Starling, its fault-tolerant machine planned for 2029. In October, IBM teams used AI coding agents to cut the estimated latency of a decoder design for that code family from 28,231 to 139 microseconds. Both figures are estimates from a design tool.
Some published loops that cross a vendor boundary ran on real qubits. In October 2024, Riverlane reported running its FPGA decoder inside the control system of a Rigetti superconducting processor. Its team measured a mean decoding time below 1 microsecond per round and a decoding response time of 9.6 microseconds.
Quantinuum’s team has decoded Helios qubits in real time on NVIDIA GPUs connected over NVQLink. NVIDIA reported a reaction time of 67 microseconds for the decoder in November 2025. Quantinuum described a larger run in March 2026 without giving a latency.
Other loops were timed without qubits. Qblox and Riverlane measured a round trip of 6.886 microseconds over QECi at distance 3, using Riverlane’s Deltaflow 2 decoder and emulated measurement data. Xanadu researchers measured a median of 2.305 microseconds between an AMD FPGA board and an AMD CPU that echoed messages back, with no quantum processor attached. In a joint post on AMD’s website, the two companies gave a mean of 2.3 microseconds for the same path.
On trapped-ion machines, the decoding deadline is three orders of magnitude longer. In their August preprint, IonQ researchers decoded a simulated machine of up to 408 logical qubits on one laptop processor, assuming error-correction cycles of 1 and 5 milliseconds. A portable kernel would have to schedule decoding against deadlines that differ by a factor of 900 to 4,500 depending on the hardware beneath it.
Calibration from milliseconds to hours
Calibration is the routine tuning of each qubit’s control signals as the hardware drifts. IBM’s documentation says that the properties the company reports for each processor are derived from calibration procedures that “typically run about once a day.” IBM also warns that “superconducting qubits, however, can drift on shorter timescales” and that “decisions based on the reported properties can depend on outdated information.” The company offers a fresh benchmark that takes “roughly 70 seconds of QPU time.”
Fabrizio Berritta, Morten Kjaergaard and colleagues used an FPGA-based controller to track a qubit’s relaxation time, the time it takes to lose its excited state, within a few milliseconds. They reported events in which it “switches by nearly an order of magnitude over timescales of just tens of milliseconds.”
Google’s team also ran repetition codes on Willow, at distances up to 29. These codes guard against only one type of error. In those runs, the team found logical performance “limited by rare correlated error events occurring approximately once every hour.”
In a December 2025 preprint, Alicia B. Magann and four co-authors, including Robin Blume-Kohout of Sandia National Laboratories, described protocols for calibrating a device during the computation and updating its settings shot by shot. In simulations of a five-qubit code, they calibrated qubits “using only syndrome data,” the error-check results that the machine already measures for error correction.
In the execution modes IBM documents, scheduling jobs on a machine means choosing between stale calibration and interrupted work. In IBM’s session mode, “no other jobs can run – including calibration jobs,” while in batch mode “QPU calibration jobs could run between the batched jobs.” The QDMI interface, built in Munich to connect quantum devices to software tools and supercomputer schedulers, caches calibration data. Its developers wrote that the cache “avoids stale data without requiring every query to incur an expensive network round-trip.”
Schedulers that cannot pause a circuit
At the top of the stack, schedulers hand out machine time to users. IBM’s architects use a library called QRMI that “offers a minimal API to be used by the resource manager (e.g., Slurm).” The Munich team describes two ways to run QDMI jobs under Slurm, one of them a plug-in that runs before each job. In its 2026 paper, the team reported a working integration only for IQM’s superconducting processors.
The designers at Riverlane and NPL put cloud access at the level whose latency exceeds the qubits’ decoherence time. A circuit sent from there runs to completion without a round trip.
Sharing one machine among several users at once remains a research topic. IBM’s authors expect quantum systems “to support multi-tenant execution” in the third and last phase of their reference architecture.
Researchers from the University of Maryland, Columbia and the University of Toronto presented HyperQ at the OSDI systems conference in 2025. HyperQ runs several programs side by side on IBM’s cloud service. Its authors wrote that HyperQ “can increase utilization and throughput while reducing program latency, by up to an order of magnitude.”
What would count as a kernel
The test this analysis applies to a quantum operating system is whether a builder can replace the processor, the control electronics or the decoder with another vendor’s part by recompiling, without custom integration, and publish timings measured on real qubits. No company had published such a result as of November 2026.
IBM’s Quantum System API is a published boundary around a real-time layer, but IBM controls both sides of it. On November 5, 2026, IBM, Oak Ridge National Laboratory and AMD launched a platform that pairs IBM’s Nighthawk processors, which have 120 physical qubits, with the laboratory’s Umbra supercomputer and AMD GPUs. IBM said the API “gives the researchers deep pulse-level capabilities.” The partners plan to compare error-correction methods by the qubits, time, samples and classical resources each requires.
In its Q Competition, a contest to speed up the development of scientifically relevant quantum computers, the Department of Energy plans a final evaluation of first-generation fault-tolerant machines in September 2028. IBM has scheduled Starling for 2029 and lists real-time decoding among its requirements.
The timing explanation for the missing layer would be overturned by a portable layer that reaches into the microsecond band across vendors. Origin Pilot or qBraid OS running another company’s control electronics would qualify, with a decoder that keeps pace with the processor’s checks and returns results in time for the operations that depend on them. Until then, a buyer who mixes vendors will pay for the integration work in rewritten code.
