IBM released a reference architecture on March 12, 2026, for combining quantum processors with the CPUs, GPUs, networks, job schedulers, and security controls of supercomputing centers. A reference architecture is a template of a system’s components and the interfaces between them, for builders to follow.
Thirteen researchers at IBM’s T.J. Watson Research Center set out the design in “Reference Architecture of a Quantum-Centric Supercomputer,” a preprint first posted to arXiv on March 11. In a press release, IBM called it “the industry’s first published quantum-centric supercomputing reference architecture.”
The authors cited early installations at RIKEN in Japan and Rensselaer Polytechnic Institute in New York as examples of the first of three phases. The second and third phases, tighter coupling between quantum and classical machines and then fully co-designed systems, are proposals in a preprint that has not been peer reviewed.
Three phases
In the first phase, the authors wrote, quantum systems “function as specialized compute offload engines within existing HPC complexes.” HPC stands for high-performance computing, the field of supercomputers and large computing clusters. An offload engine is an add-on processor that handles specific tasks for the main system.
The authors wrote that their early deployments at RIKEN, home of Japan’s Fugaku supercomputer, and at Rensselaer use Ethernet to connect the HPC systems with the quantum systems.
In the second phase, according to the authors, quantum and classical resources “become tightly coupled through advanced middleware.” For the links between machines, they named specialized interconnects such as Ultra Ethernet, NVIDIA’s NVQLink, and UALink. Middleware is the software that coordinates jobs across different machines.
In the third phase, the authors wrote, “fully co-designed quantum-HPC systems emerge,” with unified programming models and integrated system software. They wrote that they expect quantum systems to support multitenant execution around this time. Multitenant execution means several users share one machine at once.
In a research blog post, Seetharami Seelam, Antonio Córcoles, Tushar Mittal, and Jerry Chow described the design as a framework that “will progressively evolve over the next decade.”
In the preprint, the authors compared the path with the history of GPUs. Early GPU-accelerated supercomputers, they wrote, connected GPUs to CPUs over a PCIe bus, the general-purpose connection for add-in cards. In systems such as NVIDIA’s Grace Blackwell, they added, engineers now design the CPUs around the needs of the GPUs.
Scheduling and interfaces
For scheduling, the authors described the Quantum Resource Management Interface (QRMI), “a lightweight library” that presents quantum processors to the Slurm scheduler as generic resources through a plugin. Slurm is the open-source job scheduler that many supercomputing centers use to assign machines to users’ jobs. In the blog post, the IBM authors called QRMI “a thin, open-source library that abstracts away hardware-specific details.”
The authors also defined a Quantum Systems API as the only programming interface between the real-time control layer and everything else in the system. The real-time layer is the control hardware that must respond to the qubits within microseconds during a calculation.
In describing their first use case, the authors wrote that the quantum system can either be co-located with the HPC system or connected to it over the cloud.
Error correction and security
In error correction, a quantum computer spreads each logical qubit, an error-protected unit of quantum information, across many physical qubits. A decoder is the classical processor that reads error signals from those qubits and works out the corrections.
The authors split error correction into two layers. The inner layer is a code applied directly to physical qubits, with decoding and feedback in control loops of about 10 microseconds on custom electronics such as ASICs and FPGAs. ASICs are custom-designed chips, and FPGAs are reconfigurable ones.
The outer layer is a second code for further logical protection. The authors wrote that it generates error information more slowly, typically every 100 microseconds to 1 millisecond. They assigned that decoding to nearby GPU or other classical accelerator nodes.
The authors gave these timings as design parameters, not measurements.
For machines shared by several customers, the authors proposed Confidential Code and Data Encapsulation (CDE), in which users set data access controls in their programs. Under CDE, the system would split each job into tasks and run them inside trusted execution environments. A trusted execution environment is a hardware-protected area of a processor that keeps code and data isolated while they run.
The authors wrote that the security properties “should be mathematically proven,” with the proofs checked in the continuous integration pipeline. Continuous integration is the automated testing of each software change.
Use cases and timeline
The authors listed five use cases for the architecture. These are chemistry calculations by sample-based quantum diagonalization, closed-loop versions of those calculations, error mitigation with classical processing embedded in quantum workflows, open-loop error-correction research, and outer-code research for fault-tolerant error correction. Fault tolerance means a quantum computer corrects its own errors as it runs.
In sample-based quantum diagonalization, a quantum processor samples likely arrangements of a molecule’s electrons. A classical computer then calculates the molecule’s energy within that smaller set.
For closed-loop calculations, the authors cited a 2025 preprint by Tomonori Shirakawa of RIKEN and colleagues. The team passed data back and forth between an IBM Heron superconducting processor and Fugaku.
IBM said in November 2025 that it expects the first cases of verified quantum advantage to be confirmed by the wider community by the end of 2026. Quantum advantage is the point at which a quantum computer solves a problem better than any classical method. The company has set 2029 as its target for a large-scale, fault-tolerant quantum computer.
Update, November 12, 2026: On July 30, IBM and partners including the University of Chicago claimed quantum advantage in work posted as preprints. The closed-loop study by Shirakawa and colleagues has since appeared in the journal Future Generation Computer Systems.
