Silicon spin qubits are now made on 300-millimeter wafers, the size used for computer chips, in plants run by imec, Intel, and STMicroelectronics. A spin qubit stores information in the spin, a magnetic property, of one or a few electrons held in a quantum dot, a tiny region of silicon defined by voltages on metal gates. On April 20, 2026, Nature Reviews Electrical Engineering published a review in which Nard Dumoulin Stuyck, Andrew Dzurak, and eight co-authors set out where these qubits fit complementary metal-oxide-semiconductor (CMOS) manufacturing and where they depart from it. CMOS is the transistor technology inside nearly every modern chip.
Silicon qubit makers now use chip fabs for the steps that resemble making transistors, but none has yet shown that a fab can supply enriched silicon as a standard process, qubits uniform enough to be tuned automatically at scale, or control electronics within a refrigerator’s power budget at the million-qubit scale.
Six of the 10 authors listed Diraq, a Sydney company that builds silicon spin qubits, as an affiliation when they first posted the review as a preprint in September 2024. In the journal’s competing-interests statement, six authors declare equity in Diraq, among them its chief executive, Dzurak. Another author, David Reilly of the University of Sydney, leads Emergence Quantum. Two others listed affiliations with imec, the Belgian research center that fabricates Diraq’s devices.
The authors make the case for the foundry route that Diraq is taking. They also list, step by step, where that route departs from standard chipmaking. Quotations and figures attributed to the authors below are taken from their 2024 preprint, because the revised journal text is paywalled. For the journal, the authors updated the text to cite work from 2025 and 2026.
In the preprint, the authors described CMOS compatibility as a matter of degree, “ranging from the mere ability to fabricate qubits using a silicon wafer as a substrate, all the way to the co-integration of qubits with high-yield, low-power advanced electronics.” Diraq, HRL Laboratories, and Quobly each reported new silicon results between April and November 2026. Each result addresses part of the manufacturing and control problem, and none closes a gap the authors had identified at the scale of a full machine.
Steps shared with chipmaking
A gate-defined quantum dot resembles a transistor. It has a silicon channel, an insulating oxide, and gates patterned in a single plane. In the journal version, the authors attribute the fit with CMOS processes to the qubits’ submicrometer footprint, planar layout, and electrostatic control.
Diraq and imec researchers reported in Nature in September 2025 that single- and two-qubit control fidelities exceeded 99% on all four two-qubit devices they characterized from imec’s 300 mm process. Fidelity measures how closely an operation matches its intended effect. A fidelity of 99% means an average error of about 1% per operation under the benchmark used. Quantum Observer compared those results with other silicon work in March, in its article on three ways to build silicon spin qubits.
Intel released Tunnel Falls, a research chip whose 12 quantum dots “can form between four to 12 qubits,” in June 2023 and said it had made the chip on 300 mm wafers in its D1 fabrication facility. In 2024, Intel researchers reported in Nature that they had measured hundreds of devices across full 300 mm wafers at 1.6 kelvin. They used a cryogenic wafer prober, a cold version of the automated stations chipmakers use to test each chip before cutting a wafer apart.
HRL Laboratories made the controller for its silicon processor on a commercial line, in a 130-nanometer CMOS process, as Quantum Observer reported in August in its article on HRL’s controller inside the refrigerator. Quobly, a Grenoble company, said on September 16 that its team had run qubit readout and single- and two-qubit gates on one chip “fabricated in STMicroelectronics’ commercial 300 mm manufacturing facilities in Crolles.”
Where the process departs
“Qubit fabrication in CMOS typically requires breaking some of the manufacturer design rules,” the authors wrote. Design rules are the geometric and electrical limits within which a fab guarantees its process. The authors listed changes needed in a standard process, from blocking dopant diffusion and contact formation between gates to tighter gate pitch, lower gate leakage, and isotopically purified silicon and germanium.
Engineers building silicon metal-oxide-semiconductor (MOS) qubits at the densities needed for error correction also require lithography near the leading edge of logic chips. In their 2024 preprint, the authors wrote that “the commercially available 3nm FinFET CMOS technology features a gate pitch of 45 nm,” the spacing between neighboring gates. They added that recent silicon-MOS two-qubit gates of the quality needed for fault tolerance used a 30 nm pitch. The eight-qubit array that imec made for Diraq’s July paper used a 90 nm pitch.
Chipmakers insulate the gates of advanced transistors with high-k dielectrics, materials that have let chipmakers keep shrinking transistors. “Si-MOS spin qubits might suffer from the higher trap densities of high-k dielectrics,” the authors wrote. Traps are defects that capture and release electrons. Researchers call the resulting fluctuations charge noise, a source of qubit errors.
Some groups build qubits in silicon–germanium heterostructures, stacks of crystal layers with differing germanium content, instead of at an oxide interface. Those qubits need “a thick graded SiGe layer (> 1 µm),” the authors wrote. Standard CMOS lines do not include such a layer. Once the quantum well is grown, they added, a wafer cannot be processed above “around 750 °C.”
Chip designers work from process design kits (PDKs), the transistor models and rules a foundry publishes for its process. The authors called “the absence of open or freely available cryo-CMOS PDKs” a complication. They wrote that the transistor models in such kits are typically calibrated from −40 °C to +125 °C, far above the 4 kelvin or colder at which qubit controllers run.
Quobly said in September that it had developed a cryogenic design kit but did not publish its contents. Hitachi said in July that it would use “a qubit chip PDK developed by Intel” to design chips for mass production, with Intel processes based on its 18A technology.
Enriched silicon
About 4.7% of the atoms in natural silicon are silicon-29, an isotope with a nuclear spin that disturbs nearby qubits, the authors wrote. In silicon enriched in silicon-28, which has no nuclear spin, electron spins stay coherent, or keep their quantum state, about 10 times longer, they added.
Diraq and imec researchers wrote in 2025 that “residual nuclear spin-carrying isotopes contribute substantially to operational errors” in their devices. The eight-qubit array that imec made for Diraq used silicon with 400 parts per million of silicon-29 left, according to the paper. A Shenzhen team that ran logical gates on phosphorus atoms in March built its device on a layer with less than 130 parts per million, the researchers reported. Logical gates act on quantum information spread across several physical qubits so that errors can be detected or corrected.
In the 2024 preprint, the authors wrote that deposition of silicon-28 on 300 mm wafers “has been demonstrated in different R&D fabs” but that “it is currently not a commercially offered option.”
Quobly announced in December 2025 that the first custom wafers with an enriched silicon-28 layer, supplied by Soitec, had begun running through ST’s 300 mm plant for technology and process development. The company wrote that the “earliest performance metrics of these prototype devices are expected in the first quarter of 2026.” Quantum Observer found none published by November 12, 2026. The wafers use FD-SOI, short for fully depleted silicon-on-insulator, a chip technology built on a thin silicon film over an insulating layer.
Quobly said in September that its QSOI technology “was developed from the outset … including the use of enriched silicon-28.” It did not say whether the devices it tested used enriched silicon.
Variability
A CMOS fab makes billions of transistors that need only fall within statistical limits that circuit designers plan around. A spin qubit’s operating voltages and frequencies depend on atomic-scale details of its surroundings, so each one has to be tuned. The authors wrote that there is “no exact correlation between the traditional yield of CMOS transistors and the yield of the spin qubits.”
Intel said in 2023 that Tunnel Falls “provides a 95% yield rate across the wafer,” without defining the yield in its release. Intel gave a 99.8% yield for “quantum dot test chips” tuned “at the single electron level.” Intel did not say how or at what temperature it measured the 2023 yields. In its 2024 wafer-scale measurements at 1.6 kelvin, Intel’s team located where single electrons form in each device.
In Diraq’s July paper, the team tuned all eight physical qubits in the imec array but could switch on the interaction for a two-qubit gate in a controlled way on only one of the four pairs, as Quantum Observer reported in its article on the eight-qubit array. The researchers attributed the difficulty partly to “dots forming underneath the barrier gate,” the electrode between the two dots of each pair. Except for one pair whose interaction jumped suddenly, they wrote, the remaining pairs “did not show turn on with barrier gate voltage.” The paper’s authors wrote that entangling gates among qubit pairs “remain to be demonstrated.”
The review’s authors described two ways to handle variability. Makers can build qubits uniform enough to share control lines in a grid, which would cut the number of lines to about the square root of the qubit count. They can instead accept variable qubits and give each its own control circuit on the chip, an approach that may require running at a few kelvin. HRL’s researchers listed more uniform devices among the work needed to scale their processor.
Cold and control
Spin qubits reach their best fidelities at a few hundredths of a kelvin, inside dilution refrigerators. Groups have run them above 1 kelvin, the authors wrote, “albeit with somewhat reduced fidelity compared to qubit operation at milliKelvin,” without quantifying the penalty.
Engineers who wire every qubit to electronics at room temperature run out of space long before a million qubits. “Scaling above a few hundred qubits in this manner would require an impractical amount of wiring,” the authors wrote. Engineers who move the electronics into the refrigerator need fewer wires but must keep the circuits’ heat within what the refrigerator can remove.
Commercial pulse-tube cryostats offer 2 to 4 watts of cooling at 4 kelvin, the authors wrote. For a processor with a million physical qubits cooled by one such system, that leaves “less than 4 µW/qubit” for control electronics, a figure they called “a rather aggressive target.” Most demonstrations of cryogenic CMOS control “fall far short by a factor of ~1000,” they wrote in their 2024 preprint. In the journal version, they added a figure that tracks the power of cryogenic control chips over time.
HRL’s researchers ran up to seven of 18 physical qubits from a 70-million-transistor controller at 4 kelvin, with no further communication with room-temperature electronics once a program started, according to their Nature paper. The controller draws 3.5 watts or less in typical operation, the team wrote in its preprint. That is about the whole 4-kelvin budget that the review’s authors allowed for the control electronics of a million qubits. The team listed “controllers with even lower power consumption per qubit” among the advances still needed.
At the colder end, a team led by Reilly, a co-author of the review, reported a CMOS control chip of about 100,000 transistors working at millikelvin temperatures beside qubits supplied by Diraq. Four other review authors, Will Gilbert, Dumoulin Stuyck, Christopher Escott, and Dzurak, co-wrote the chip paper. The researchers wrote in Nature in 2025 that “milli-kelvin control has little impact on the performance of single- and two-qubit gates.” They ran two qubits and wire-bonded 2 of the chip’s 32 control cells to the device’s gates.
The University of Sydney said in June 2025 that the chip ran within “a power envelope of just 10 microwatts.” The paper’s authors wrote that the chip’s digital circuits account for “a fixed overhead power of tens of microwatts.” The university also said that Reilly’s company, Emergence Quantum, was “established this year to commercialise quantum control technologies.”
The researchers made the strongest published case that such control can scale. They wrote that the chip has “a power density sufficiently low to enable scale-up,” enough for “many thousands of cells” to fit within a dilution refrigerator’s cooling budget of “around 1 mW at 100 mK.” Many thousands of cells would still fall short of the million qubits in the review’s budget.
Reading a “CMOS-compatible” claim
Diraq wrote on April 28, eight days after the review appeared, that “CMOS compatibility exists on a spectrum.” In three announcements since September 2025, companies named a 300 mm or standard CMOS process without reporting gate fidelities for the devices they described.
On July 13, imec and Diraq announced the “first coherent operation of eight silicon MOS spin qubits fabricated in a 300mm CMOS-compatible foundry process.” In the paper behind it, the researchers reported coherence for all eight physical qubits, the one working pair, and no gate fidelities for the array.
In September 2025, Quantum Motion, a London company, described its system at the UK’s National Quantum Computing Centre (NQCC) as the “first full-stack quantum computer to be built using a standard silicon CMOS chip fabrication process.” The company gave no qubit count or fidelities in the release. The NQCC published no measurements of the system in its October 21, 2026, testbed report. The report’s section on the system says the NQCC team “will validate and benchmark this device.”
Quobly reported readout and gates on its chip from ST’s Crolles plant without a qubit count, an operating temperature, or fidelities. “Further details and performance metrics will be reported in a forthcoming scientific publication,” the company wrote.
A reader can place most such claims on the spectrum by finding five facts in the paper behind each one.
- Which steps ran on a production line, and which design rules the team broke
- Whether the silicon was natural or enriched, and how much silicon-29 remained
- The temperature at which the qubits were measured, and where the control electronics were mounted
- What a yield figure counts, whether dots that form or qubits that pass a fidelity test
- Whether fidelities came from the array itself or from separate two-qubit devices
The case for the foundry route
Diraq and the review’s authors make the case for the foundry route with data. Diraq wrote in April, “Four separate devices on the same wafer, selected at random, all exceeded the fault-tolerance threshold,” the fidelity level above which error correction can suppress errors in a given code and noise model. It added, “This result was only possible because the technology is truly native to the commercial manufacturing process.” The company has said it aims to reach utility scale, the point at which a machine’s computational value exceeds its cost, by 2031 with more than 2 million physical qubits on a single chip.
IBM, Intel, and the Defense Advanced Research Projects Agency (DARPA) each backed silicon spin qubits in 2026. IBM said its purchase of HRL offered “potential plans to develop spin qubit manufacturing” with Anderon, its planned quantum wafer foundry, and completed the deal on August 26. Intel agreed on October 26 to buy Classiq, a quantum software company, to pair Classiq’s software with Intel’s silicon spin-qubit technology in a full-stack platform, as Quantum Observer reported in its article on the Classiq deal. DARPA advanced Diraq to the final stage of its Quantum Benchmarking Initiative on October 7, as Quantum Observer reported in its article on the Stage C selections.
Fabs do supply silicon groups with process control at 300 mm, wafer-scale testing, and control chips made on commercial production lines. Makers of other qubit types point to fabs as well. IonQ, which builds trapped-ion computers, said in September that it had fabricated its first “fully integrated 256-qubit quantum processing units” at its subsidiary SkyWater. IBM plans to make superconducting wafers first at Anderon, which it is setting up in Albany, New York.
In the review’s own terms, silicon’s distinctive claim is the far end of the spectrum, qubits and their control electronics made together at scale. Quobly says it has made qubits and cryogenic circuits on the same chip.
Diraq’s and HRL’s teams each stopped at a gap the authors had listed. For Diraq, the gap was variability across the eight-qubit array. For HRL, it was the controller’s power.
Next tests
Hitachi, working with Intel’s Japanese subsidiary and Japan’s National Institute of Advanced Industrial Science and Technology, aims to build prototype silicon quantum computers “implementing quantum error-correcting codes at the 100-qubit scale” in fiscal 2028, without saying whether it counts physical or logical qubits. It aims for the 1,000-qubit scale in fiscal 2030. Diraq disclosed a first Stage C tranche of $51 million. The company said the money “will support the next year of Diraq’s path to a utility-scale, fault-tolerant quantum computer.”
Silicon makers would need four results to turn “CMOS-compatible” into a claim about scale. The first is fidelity statistics for hundreds of physical qubits from one wafer, measured at operating temperature, with the time and automation needed to tune them. The second is a foundry that offers enriched silicon and a cryogenic design kit as standard process options.
The third is control electronics that run hundreds of qubits without loss of fidelity and draw power within about tenfold of the 4-microwatt-per-qubit budget. The fourth is a silicon error-correction experiment in which the logical error rate falls as the code grows, for both bit-flip and phase-flip errors. HRL’s team corrected one of the two kinds with a repetition code, the simplest error-correcting code. The Shenzhen team detected errors with its code but did not correct them.
Diraq and imec have reported fidelities above 99% on separate two-qubit devices. If Diraq, Intel, or Quobly publishes fidelities at that level for an array of dozens of physical qubits from a production line, that company will have narrowed the gap between compatibility and scale in the way the review’s authors expect.
An earlier version of this analysis appeared on PostQuantum.com, the author’s own publication, on April 21, 2026. It is republished here with permission and was revised and updated for Quantum Observer in November 2026.
