Researchers from UNSW Sydney, the Australian company Diraq, and the Belgian research institute imec reported in Nature Communications on July 9, 2026, that they had tuned and coherently controlled a linear array of eight physical silicon spin qubits. A spin qubit stores information in spin, a magnetic property of electrons. The paper’s 27 authors, who include researchers at Ghent University and KU Leuven, first posted the results as a preprint in December 2025 and revised it on June 1, 2026, a week before the journal accepted the paper.
In the paper, the authors wrote that imec designed and fabricated the device with a 300 mm silicon fabrication process. Here, 300 mm is the diameter of the silicon wafers, the size used in high-volume chip manufacturing. The process is compatible with CMOS, the standard technology for making computer chips.
The team reported coherence for all eight qubits and a two-qubit gate on one of the array’s four qubit pairs, with no gate fidelities for the array. Coherence is a qubit’s ability to keep its quantum state. Gate fidelity is a measure of how accurately a qubit operation, or gate, runs.
The device
The chip is a chain of eight quantum dots, tiny regions of silicon that trap electrons. The researchers loaded each dot with an odd number of electrons, from one to nine. In each dot, the electrons behaved together as a single spin, which the team used as a physical qubit. The authors wrote that the dots were defined by gate electrodes at a 90 nm pitch on silicon enriched to leave 400 parts per million of silicon-29. The nuclear spin of silicon-29 is a main source of magnetic noise for these qubits.
The researchers operated the chip at about 20 mK, two hundredths of a degree above absolute zero, in a magnetic field of 0.5 T. They tuned all eight qubits and characterized them as four pairs of neighboring dots.
The Ramsey coherence time is a measure of how long an idle qubit keeps its phase. The authors reported Ramsey times of up to 41 µs, with an average of 21 µs across the eight qubits. With an added pulse that cancels slow noise, they measured Hahn-echo times of up to 1.31 ms and an average of 0.7 ms.
The authors wrote that these values are comparable to those reported for devices made with a similar foundry process. They also wrote that the results exceed those from devices fabricated in academic facilities.
Readout from the ends of the chain
The chip has two single-electron transistors, charge sensors that register the movement of individual electrons, one at each end of the array. The researchers read out the four central qubits with a cascaded charge-sensing protocol. In that scheme, a spin-dependent electron movement in a central pair sets off a chain of charge shifts that the end sensors detect.
The authors described the result as high-fidelity measurement of the whole array in a two-step process.
One working pair
The team demonstrated a controlled-phase (CZ) gate, an operation that entangles two qubits, on the pair at one end of the chain, with low phase noise. The gate relies on exchange, an interaction between neighboring electrons that the researchers switch on with a voltage on the barrier gate between them.
In the other three pairs, exchange did not turn on in a controlled way. In the two central pairs, an electron tunneled into a spurious quantum dot before exchange appeared, the authors wrote. In the pair at the other end, exchange increased suddenly.
The authors wrote that entangling gates among the qubit pairs “remain to be demonstrated,” a step they need to verify their approach of tuning the array pair by pair.
Fidelities
The authors reported no gate fidelities for the eight-qubit array. The same collaboration reported fidelity figures for a similar imec foundry process in a September 2025 Nature paper on four two-qubit devices.
In that paper, the researchers reported single- and two-qubit control fidelities above 99% on all four devices, with state preparation and measurement fidelities of up to 99.9%. They measured those figures with gate set tomography, a method for reconstructing each operation’s errors from many sequences of gates. Quantum Observer compared those results with other silicon spin qubit work in March.
Next steps and funding
The authors wrote that scalable, fault-tolerant error-mitigation routines for spin qubits require higher-order qubit connectivity, such as bilinear arrays, made of two parallel rows of qubits. A fault-tolerant computer corrects its own errors as it runs. The authors also wrote that further progress in fabrication, including refined lithographic techniques, will be necessary.
DARPA, the Defense Advanced Research Projects Agency, selected Diraq in November 2025 for Stage B of its Quantum Benchmarking Initiative, a review it described as yearlong. DARPA said companies that succeed in Stage B will be invited to the final stage, in which a government team verifies whether a company’s utility-scale quantum computer can be “constructed as designed and operated as intended.” The agency defines utility-scale operation as computational value exceeding cost.
In May, the U.S. Department of Commerce signed a letter of intent with Diraq for up to $38 million in planned CHIPS funding to develop and scale quantum logic units. In a letter of intent, the parties outline the terms of a deal before they sign a binding agreement.
Update, November 12, 2026: In a joint July 13 release, imec and Diraq claimed the “first coherent operation of eight silicon MOS spin qubits” made in a 300 mm, CMOS-compatible foundry process. On October 7, Diraq said DARPA had selected it to advance to Stage C, with funding of up to US$300 million and an initial tranche of US$51 million.
